China’s chip self-sufficiency stalls at 34 percent despite breakneck expansion

China’s supply of advanced-node wafers will grow at a compound annual rate of 46% through 2035, cutting its domestic shortfall for 7‑nanometer‑and‑below chips from 92% to 34%, Goldman Sachs projects in a new decade‑scale forecast. Even at that speed, the country would still need outsiders for more than a third of its most advanced wafers at the end of the period.

The model quantifies both the breakneck expansion at SMIC, China’s largest foundry, and the wall that export controls have built: lithography equipment, especially EUV tools made only by ASML, remains blocked. To close the gap, SMIC would need yields to triple by 2035 — from 23 % to 75 %.

China’s push to build an indigenous advanced‑chip industry will slash its dependence on imported wafers to 34 % by 2035 — a dramatic improvement that still leaves more than a third of its 7‑nanometer‑and‑below supply reliant on outsiders, according to a new forecast from Goldman Sachs.

The forecast models domestic wafer output growing at a compound annual rate of 46 % through 2035, while demand rises more slowly. But the central finding is that EUV lithography — machines made only by the Netherlands’ ASML and barred from Chinese fabs by US‑led export controls — keeps full self‑sufficiency out of reach. SMIC must triple its yields over the decade, to 75 %, even as it adds up to 50 000 wafers of monthly capacity each year. That arithmetic leaves a gap no amount of money can currently close.

The production ramp that still leaves a hole

Goldman’s model breaks the decade into two expansion phases. From 2026 through 2031, SMIC adds 30 000 to 50 000 advanced‑node wafers of monthly capacity every year. After 2031, the annual addition slows to 20 000 wafers per month. By 2035, China’s total advanced supply reaches 410 000 wafers a month, against projected demand of 619 000. The 46 % supply growth rate runs well ahead of the 17 % expected demand growth, which is why the gap narrows — but not enough to close.

The yield climb is similarly steep. The model assumes SMIC’s yields improve from 23 % in 2026 to 50 % in 2030 and 75 % by 2035. By comparison, TSMC has been mass‑producing 7 nm chips since 2018 and routinely achieves yields above 90 %. For a Chinese smartphone maker designing a next‑generation AI chip, every wafer allocated by TSMC or Samsung is a wafer they cannot source from SMIC — and the price premium is still worth paying.

Beijing has constructed a working EUV prototype in a high‑security laboratory in Shenzhen. Independent analysts see commercially viable production from Chinese‑developed lithography as unlikely before 2030, and most stress that the gap between a pilot machine and an economically sustainable, high‑volume system is measured in years, not months. Liu Peizhen of the Taiwan Economic Research Institute has stated that China’s domestic 7nm production has largely reached its current limits because of constraints in advanced lithography, and that meaningful breakthroughs beyond 7 nm are unlikely for at least five years, leaving the 34 % gap as a floor, not a peak.

The sequence below shows how each step in advanced chipmaking compounds China’s tooling problem.

Goldman Sachs chief China economist Hui Shan has argued that Beijing’s heavy emphasis on high-tech manufacturing and technological innovation is unlikely by itself to generate stronger household incomes or consumption, given manufacturing’s limited share of employment. The industrial strategy can build fabs, she suggests, but the productivity gains may not flow through to households at the scale needed to sustain domestic chip demand over the long run.

The gap that policy designed

The U.S. Commerce Department updated its semiconductor export controls in October 2023 and clarified them in April 2024, tightening restrictions on advanced computing chips and manufacturing tools for Chinese fabs. The Netherlands imposed licensing requirements on ASML’s DUV and EUV systems through 2024, effectively blocking the most advanced tools. These rules define the ceiling on China’s yields and, by extension, on its output.

While Washington’s moves get the headlines, the Chinese government’s response is equally structured. A 2025‑2026 action plan for the electronics industry explicitly links import substitution in semiconductors to supply‑chain security, signalling that state funding and procurement mandates will cushion low‑yield fabs for years. That insulation from commercial discipline is the parallel with the U.S. CHIPS Act, but with a critical difference: China’s firms cannot buy the best lithography, so the subsidies are chasing a capability that the equipment market denies them.

The global foundry numbers underscore the distance. TSMC held 72 % of pure‑play foundry revenue in the third quarter of 2025, with Samsung at 11.5 % and SMIC at 5.7 %. Advanced processes at 7 nm and below generated 74 % of TSMC’s wafer revenue in the fourth quarter. SMIC is climbing a mountain built by two companies that have had unfettered tool access for a decade.

The 34 % gap is therefore a policy outcome, not a market accident. Without licensing relief or a commercially viable domestic EUV system — a late‑2030s prospect, according to Dylan Patel of SemiAnalysis — China’s advanced‑chip expansion hits a ceiling calibrated in Washington and The Hague, not Beijing. The next test is whether upcoming negotiations with the Netherlands and Japan over the next six to twelve months shift any of those parameters; if they do not, the gap Goldman projects will be the permanent floor for China’s advanced‑chip dependence.

Beyond the headline

The bigger picture

China’s projected narrowing of its advanced‑node deficit sits within a broader realignment where mature‑node dominance and state‑backed capacity are becoming as strategically important as true leading‑edge manufacturing. For Western firms, this means that even if China never matches TSMC at 3 nm, its growth in 7 nm‑class and mature chips can still reshape pricing, supply security and the geography of industrial and defence electronics.

The timing

Goldman’s long‑range forecast arrives just as global semiconductor demand surges toward a potential USD 1 trillion market in 2026 and as US‑led export controls move from initial shock to steady‑state constraints. This timing matters because it shows Beijing planning around sanctions rather than awaiting relief: China’s capacity build‑out is being calibrated to a world where tooling restrictions persist, not one where they quickly unwind.

What isn’t being said

Most discussion of China’s advanced‑node ambitions focuses on lithography, but less attention is paid to the economic viability of low‑yield nodes and the political durability of state subsidies sustaining them. If policy‑driven demand, generous financing and local procurement mandates remain in place, sub‑scale, high‑cost advanced fabs can survive for years — meaning Western firms face a competitor insulated from normal commercial discipline at precisely the nodes that feed AI and defence applications.

What the 34 % gap means for different players

With export control architecture stable but under periodic review, here is how readers with direct stakes in the semiconductor supply chain should absorb Goldman’s numbers.

• Western semiconductor procurement manager

  Your future sourcing strategy must account for Chinese‑made advanced wafers becoming a larger piece of global supply, especially for 7 nm‑class designs that fall outside the most restrictive nodes. Monitor SMIC’s yield improvements and any loosening of Dutch DUV licenses — both could reshape cost comparisons. Start mapping which of your designs could run on a Chinese foundry without violating export controls, using the Bureau of Industry and Security’s public updates on advanced computing rules.

• US‑based investor with APAC emerging market exposure

  Re‑evaluate positions in Chinese foundry equities and Taiwanese leaders. The forecast implies SMIC’s annual advanced‑node revenue could grow sharply if yields follow the projected curve, but the gap also caps its ability to capture the highest‑margin business. TSMC’s lead in 3 nm and below appears durable, so the risk is not displacement but margin compression in mid‑advanced nodes. Watch ASML’s quarterly disclosures on DUV licensing to China for the earliest signal of capacity acceleration.

• US government policy advisor on export controls

  Goldman’s model gives you a quantified baseline for whether current controls are achieving their aim. The rapid supply growth suggests that restrictions on EUV work but leave room for significant capacity expansion via multi‑patterned DUV. Consider tightening rules on DUV maintenance and spare parts as the next policy lever, and watch the Chinese action plan for targets that reveal where Beijing expects to substitute imports.

• Executive at a Western advanced chip design firm

  A growing pool of Chinese‑sourced 7 nm‑class wafers, even at lower yields, means new fabless‑foundry partnerships could emerge inside China over the next five years. Map your product lines that can tolerate relaxed defect‑density specs and consider whether a China‑based porting option becomes viable before 2030. The competitive risk is not immediate, but the trajectory says your Chinese rivals will have increasing access to a domestic advanced platform — plan your node‑migration timelines accordingly.

Explainer

EUV

Extreme ultraviolet lithography uses light with a wavelength of roughly 13.5 nanometres to pattern transistor features on a silicon wafer. The machines, made exclusively by the Netherlands’ ASML, are the only commercially viable way to produce chips at 7 nm and below with high yield. China’s access to EUV tools is blocked by multilateral export controls, forcing its fabs to use older DUV systems with multi‑patterning that increases cost and defect rates.

DUV

Deep ultraviolet lithography uses light with a wavelength of 193 nanometres and is the workhorse for a wide range of semiconductor nodes. At 7 nm and below, DUV requires multiple patterning passes to achieve the same resolution as a single EUV exposure, multiplying the number of lithography‑etch cycles and lowering the fraction of usable chips per wafer. China’s fabs are largely confined to DUV, which is why their advanced‑node yields lag TSMC and Samsung.

Semiconductor yield

Yield measures the percentage of chips on a silicon wafer that function correctly and meet performance specifications after manufacturing. Advanced nodes start with very low yields; TSMC’s 7 nm process reached mature yields above 90 % after years of refinement. Goldman’s model assumes SMIC’s 7 nm yield rises from 23 % in 2026 to 75 % in 2035, a trajectory that depends on process learning and equipment that remains under export restrictions.

SMIC

Semiconductor Manufacturing International Corporation is China’s largest contract chipmaker, based in Shanghai. It operates fabs capable of producing 7 nm chips but relies on multi‑patterned DUV tools rather than EUV, limiting both yield and the number of advanced wafers it can economically produce. The Goldman Sachs forecast hinges on SMIC expanding its monthly advanced‑node capacity by 30 000 to 50 000 wafers per year through 2031.

TSMC

Taiwan Semiconductor Manufacturing Company is the world’s largest pure‑play foundry, headquartered in Hsinchu, Taiwan, and supplies the majority of the world’s most advanced processors. It began mass‑producing 7 nm chips in 2018 and now generates nearly three‑quarters of its wafer revenue from processes at 7 nm and below, including 3 nm nodes deployed in the latest smartphones and AI accelerators.